1. Technical Field
The present invention relates in general to a method and system for data processing and, in particular, to a processor and method for generating a memory request address in a processor. Still more particularly, the present invention relates to a processor that decodes multiple instructions, generates, in parallel, a fetch address from each decoded instruction, and then selects one of the generated fetch addresses as a memory request address.
2. Description of the Related Art
A processor may include an instruction queue from which instructions are dispatched to one or more execution units for execution and an instruction fetcher that calculates fetch addresses and uses the fetch addresses to retrieve instructions from memory to fill the instruction queue. In a conventional processor, priority logic is utilized to determine which instruction in the instruction queue should be utilized to generate the next fetch address. Following selection of an instruction by the priority logic, a fetch address is generated from the instruction, typically by adding an instruction-length offset to the address of the selected instruction. The fetch address generated from the selected instruction is then passed to a memory as a request address in order to obtain one or more instructions stored at the memory location specified by the request address. Thus, the conventional instruction fetch cycle is comprised of a number of steps that are performed sequentially.
The time interval beginning with the examination of instructions in the instruction queue and ending with the receipt of the fetched instructions from memory may be referred to as the instruction fetch cycle time. In efforts to decrease a processor's instruction fetch cycle time and therefore enhance the overall performance of the processor, attention is typically focused on improving the design and configuration of the individual components of the memory, for example, by adopting faster memory technologies, improving instruction cache hit rates, and incorporating additional levels of cache on-chip with the processor. While these solutions certainly can improve instruction fetch cycle time, the present invention includes a recognition that instruction fetch cycle time can also be decreased by parallelizing steps within the instruction fetch cycle.